This invention relates to isolation of insulated-gate field effect transistors (hereinafter referred to as MOS transistors) and more particularly to isolation of complementary MOS (hereinafter referred to as CMOS) transistors formed on a substrate in a high density.
Integrated circuit devices using CMOS transistors are featured in low power consumption and high noise margin. Higher integration density of CMOS devices has been attained in recent years and a large number of proposals have been made on the isolation structure of CMOS ULSI devices. Kasai et al. have disclosed such isolation structure in their article "1/4.mu.m CMOS Isolation Technique Using Selective Epitaxy"(IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. ED-34, No. 6, Jun. 1987, pp. 1331-1336). The disclosed technique comprises forming a trench in a p-type silicon substrate, forming 1/4.mu.m thick insulator films for device isolation on the sidewalls of the trench, which are shaped perpendicular to the substrate surface plane, refilling the trench with selectively grown single-crystal silicon thereby to provide an n-well, and fabricating a n-channel MOS transitor on the p-type substrate and a p-channel MOS transistor on the n-well.
In the prior art technique described above, the device isolation region can be made narrow by reducing the thickness of the insulator film formed on the trench sidewall without relying on resolution of the lithography process. However, the MOS transistors fabricated are of the conventional planar type and it has been difficult to reduce the occupying area of the MOS transistors.